The present disclosure relates to multi-phase clock divider circuits capable of accurately dividing the frequency of a multi-phase clock signal which oscillates at a high frequency while maintaining the phase relationship of the signal.
In recent years, flash memories, which are a non-volatile semiconductor memory device, have required data to be read and rewritten with a single power supply voltage or a low power supply voltage, and the flash memory requires, on the same chip, a booster circuit which supplies a boosted voltage or a negative boosted voltage when each operation is performed.
There is a technique of reducing the circuit area of the booster circuit by operating the booster circuit in accordance with a boost clock signal having a higher frequency. On the other hand, after a predetermined voltage is output as the boosted voltage, a technique of operating the boost clock signal at a low frequency is required so as to reduce noise, current consumption, and the like. Moreover, a multi-phase clock signal is used in the booster circuit, and the phase relationship of the signal has a key role in the boost operation. Therefore, a multi-phase clock divider circuit is required which can divide the frequency of the multi-phase clock signal oscillating at a high frequency while maintaining the phase relationship of the signal.
FIG. 13 shows a configuration of a divider circuit described in Japanese Patent Publication No. 2001-350539. The divider circuit 900 includes latch circuits DFF<0>-DFF<7> which receive a multi-phase clock signal including clock signals CLK<0>-CLK<7> and output frequency-divided clock signals FCK<0>-FCK<7> having multiple phases, and logic elements NR<0>-NR<6> which receive the inverted output NQ of the latch circuit DFF<I>(0≦I≦6) and the output Q of the latch circuit DFF<I+1> and generates a data signal to the latch circuit DFF<I+1>. Only the latch circuit DFF<0> receives the inverted output NQ of itself as its data signal.
Next, operation of the divider circuit 900 of FIG. 13 will be briefly described with reference to FIG. 14.
[Time T0: Initial State]
Initially, at time T0, the outputs Q (the frequency-divided clock signals FCK<0>-FCK<7>) of the latch circuits DFF<0>-DFF<7> are “low” (logical low level), and the inverted outputs NQ are “high” (logical high level). Therefore, the data signals DT0-DT6 of the logic elements NR<0>-NR<6> are fixed low. During a period that the data signals DT0-DT6 are low, the outputs Q (the frequency-divided clock signals FCK<0>-FCK<7>) of the latch circuits DFF<0>-DFF<7> are fixed to low irrespective of the inputs of the clock signals CLK<1>-CLK<7>. On the other hand, the input data signal of the latch circuit DFF<0> is the inverted output NQ of itself and therefore is high.
[Time T1]
At time T1, the clock signal CLK<0> goes high, so that the output Q of the latch circuit DFF<0> goes high and the inverted output NQ goes low. As a result, the frequency-divided clock signal FCK<0> goes high, and the data signal DT0 goes high and is input to the latch circuit DFF<1>, which receives the data signal DT0 in a high-data latch time Tlatr or less. Here, the high-data latch time Tlatr is (1/clock frequency fosc)/number of phases in the multi-phase clock signal. For example, when the clock frequency fosc=100 MHz and the number of phases in the multi-phase clock signal=8, the high-data latch time Tlatr=1.25 ns.
[Time T2]
At time T2, the clock signal CLK<1> goes high, so that the data (DT0=high) received by the output latch circuit DFF<1> is output, and the output Q goes high and the inverted output NQ goes low. As a result, the frequency-divided clock signal FCK<1> goes high, and the data signal DT1 goes high and is input to the latch circuit DFF<2>, which receives the data signal DT1 in the high-data latch time Tlatr or less. At the same time, the data signal DT0 goes low.
Subsequently, at times T3-T8, frequency division is similarly performed by the latch circuits DFF<2>-DFF<7>. During this time period, at time T6, the clock signal CLK<1> goes low, so that the latch circuit DFF<1> receives the data signal DT0 (=low) input to the data terminal D in a low-data latch time Tlatf or less. Here, the low-data latch time Tlatf is independent of the number of phases in the multi-phase clock signal and dependent largely on the clock frequency, and is almost equal to (1/clock frequency fosc)/2. For example, when the clock frequency fosc=100 MHz, the low-data latch time Tlatf=5 ns. Subsequently, similar operation is performed at times T9-T17.